FIG. 1 (Prior Art) is a diagram of a network interface device (NID) 100 that couples a host computer 101 to a network 102. The particular NID 100 of FIG. 1 is an expansion card that is coupled to host computer 101 via PCI bus 103. NID 100 includes an integrated circuit 104, physical layer interface circuitry 105, and dynamic random access memory (DRAM) 106. Integrated circuit 104 includes a media access controller 107, queue manager hardware 108, a processor 109, sequencers 110, an SRAM controller 111, static random access memory (SRAM) 112, a DRAM controller 113, a PCI bus interface 114, a DMA controller 115, a DMA command register 116, and a DMA command complete register 117. For additional detail on one such integrated circuit 104, see U.S. patent application Ser. No. 09/464,283, filed Dec. 15, 1999 (the subject matter of which is incorporated herein by reference).
In one example, NID 100 is used to retrieve three portions of data 118–120 from host storage 121 and to output them to network 102 in the form of a data payload of a packet. In the situation where the three portions 118–120 are stored on different pages in host storage 121, it may be necessary to move the data to DRAM 106 individually. The three portions 118–120 are to all be present in DRAM 106 before packet transmission begins.
In the device of FIG. 1, processor 109 causes DMA controller 115 to execute DMA commands 122 by placing the DMA commands into SRAM 112 via lines 123 and SRAM controller 111. Once a DMA command is present in SRAM 112, processor 109 instructs the DMA controller to fetch and execute the DMA command by setting a bit in DMA command register 116. A DMA command includes a source address for data to be moved, a destination address for data to be moved, and a byte count. In the example of FIG. 1, there can be thirty-two pending DMA commands 122 stored in SRAM 112. Consequently, there are thirty-two bits in DMA register 116. DMA controller 115 fetches the command, executes the command, and then sets a corresponding bit in 32-bit DMA command complete register 117. Processor 109 monitors the bit in the DMA command complete register 117 to determine when the DMA command has been completed.
In the example of FIG. 1, each of the three data portions 118–120 is moved into DRAM 106 in two moves. In a first move, the data is moved from host storage 121 and to a buffer in SRAM 112. In a second move, the data is moved from the buffer in SRAM 112 and to DRAM 106.
To move the first portion of data 118 from host storage 121 to DRAM 106, processor 109 writes a DMA command into SRAM 112. DMA controller 115 retrieves the DMA command from SRAM 112 via SRAM controller 111 and lines 124. DMA controller 115 then executes the command by sending a request to PCI bus interface 114 via lines 125. PCI bus interface 114 responds by retrieving data 118 from a particular address X1 and supplying that data to SRAM controller 111 via lines 126. PCI bus interface 114 reports completion of this action by returning an acknowledge signal to DMA controller 115 via line 127. SRAM controller 111 writes the data into the buffer in SRAM 112. DMA controller 115 then issues a request to DRAM controller 113 via lines 128. Data from SRAM 112 is then transferred via SRAM controller 111, lines 129, and DRAM controller 113 to a location 130 (address Z1) in DRAM 106. When this action is complete, DRAM controller 113 returns an acknowledge signal to DMA controller 115 via line 131. DMA controller 115 sets a bit corresponding to this completed DMA command in the DMA command complete register 117. In this way, each of the three portions of data 118–120 is moved through SRAM 112 and into DRAM 106. Although the three data portions are illustrated being stored in DRAM 106 at different locations Z1, Z2 and Z3, this need not be the case. All three data portions are sometimes stored in one continuous block.
In the particular NID 100 of FIG. 1, DMA controller 115 may execute DMA commands in an order different from the order in which the DMA commands were placed in SRAM 112 by processor 109. For example, while DMA controller 115 is moving the first portion 118 to DRAM 106, the processor 109 may place additional DMA commands into SRAM 112. When DMA controller 115 finishes moving first portion 118, the DMA controller 115 may fetch a DMA command to move the third portion 120 next. Because all three data portions 118–120 are to be in DRAM 106 before transmission of the packet begins, processor 109 cannot only check that the last move in the sequence is completed. Rather, processor 109 must check to make sure that all the moves are completed before processor 109 goes on in its software to execute the instructions that cause the ultimate packet to be formed and output from NID 100.